The invention relates to a semiconductor device comprising a semiconductor body the surface of which is provided with an insulating layer and which comprises, in succession, a substrate of a first conductivity type, a first semiconductor region of a second conductivity type which is opposite to the first conductivity type, which semiconductor region forms a collector region of a bipolar transistor and is provided with a first connection conductor, a second semiconductor region of the first conductivity type, which forms a base region of the transistor and is provided with a second connection conductor, and a third semiconductor region of the second conductivity type which forms an emitter region of the transistor and is provided with a third connection conductor, at least one of the connection conductors extending over a part of the insulating layer below which there is a further semiconductor region of the second conductivity type. Such a device constitutes, or forms part of, for example an amplifier. The invention also relates to a method of manufacturing such a device.
A device of the type mentioned in the opening paragraph is known from United States patent specification U.S. Pat. No. 5,107,320, published on Apr. 21, 1992. FIG. 3 of said patent specification shows a substrate on which a bipolar transistor with a collector region, base region and emitter region is provided. The surface of the semiconductor body of the device is covered with an insulating layer over which a part of the connection conductors of the device extends. The capacitance between this part of the connection conductors and the substrate, the so-called interconnect capacitance, limits the speed of the transistor. Below the insulating layer and above the substrate there is a further semiconductor region of a conductivity type which is opposite to that of the substrate. The pn-junction thus formed forms an additional series capacitance with respect to the capacitance of the insulating layer. In this manner, an important reduction of the overall capacitance between the connection conductors and the substrate can be achieved.
A drawback of the known device resides in that it is less suitable for certain applications, particularly for use as or in a power amplifier.
Therefore, it is an object of the invention to provide a device which is very fast and which does not exhibit the above-mentioned drawback, or only to a limited extent, and which can suitably be used in or as a power amplifier. The invention also aims at providing a simple method of manufacturing said device. To achieve this, a device of the type mentioned in the opening paragraph is characterized in accordance with the invention in that a part of the further semiconductor region adjoining the substrate is provided with a doping concentration which is higher than that in the remaining part of the further semiconductor region.
The invention is based on the following surprising recognitions. In the first place, the recognition that a low doping concentration of the further semiconductor region does lead to a maximum reduction of the interconnect capacitance, but also that such a layer comprises relatively few charge carriers. During operation of the device this may lead to complete depletion of the further semiconductor region. In practice this means that a short-circuit occurs between the connection conductor and the substrate. The equivalent loss resistance then becomes 0 Ohm, which is undesirable, particularly for the output of a power amplifier wherein the voltage across this capacitance is very high. In the case of a high doping concentration of the further semiconductor region this drawback does not occur, but the pn-junction between this region and the substrate, which is relatively high in this case, leads to almost no reduction of the interconnect capacitance. By dividing the further semiconductor region into a (lower-level) part having a higher doping concentration and a (higher-level) part having a lower doping concentration, both problems, namely the problem of a high interconnect capacitance and the problem of too low an equivalent loss resistance can be precluded. By providing the lower-level part of the further semiconductor region with a higher doping concentration, it is achieved that the higher-level part can also fulfill the function of a lower-doped part of the collector region, so that both parts can be manufactured simultaneously. In addition, this construction also enables the higher-doped, lower-level part of the further semiconductor region to be manufactured at the same time as a higher-doped, lower-level part of the collector region. This is an important additional advantage. All this will be explained in greater detail hereinbelow.
In a preferred embodiment, the part of the collector region adjoining the substrate has a higher doping concentration than the rest of this region, and the doping concentration of the part of the further semiconductor region adjoining the substrate is lower than the doping concentration of the part of the collector region adjoining the substrate. This enables the collector region and the further semiconductor region to function optimally, as well as the part of the further semiconductor region adjoining the substrate to be manufactured at the same time as the part of the collector region adjoining the substrate, namely by making the lower-level part of the collector region extend, in a modulated manner, at the location of the further semiconductor region. This is achieved by dividing the lower-level part of the collector region into sub-regions at the location of the further semiconductor region. A suitable thermal treatment will cause these regions to merge, thereby forming a continuous homogeneous layer having a lower doping concentration than the lower-level part of the collector region. As a result, however, the doping concentration of the lower-level part of the further semiconductor region will be slightly laterally modulated. However, this does not interfere with the intended, above-discussed effects.
In a very favorable embodiment of a device in accordance with the invention, the semiconductor body is provided with another semiconductor region of the first conductivity type, which is recessed in said semiconductor body, and which is connected to the substrate, and provided with another connection conductor and situated, preferably, as close as possible to the active region of the transistor. In this manner, the above-mentioned losses which occur, in particular, when the device is used in or as a power amplifier are further limited in a very practical manner because the substrate resistance, which is connected in series to the interconnect capacitance(s), is as close to zero as possible. Such a construction is very surprising, particularly for a discrete transistor wherein the collector region generally coincides with the substrate, and for the intended purpose, i.e. minimizing the losses of a transistor.
Consequently, the device thus formed is very fast and can very suitably be used in or as a power amplifier, particularly for an end stage thereof.
A method of manufacturing a device in accordance with the invention, wherein, in a semiconductor body the surface of which is provided with an insulating layer and which is formed by means of a substrate of a first conductivity type, there are formed in a side-by-side relationship, a first semiconductor region of a second conductivity type, which is opposite to the first conductivity type, which forms a collector region of a bipolar transistor and is provided with a first connection conductor, a second semiconductor region of the first conductivity type which forms a base region of the transistor and is provided with a second connection conductor, and a third semiconductor region of the second conductivity type, which forms an emitter region of the transistor and is provided with a third connection conductor, at least one of the connection conductors extending over a part of the insulating layer below which a further semiconductor region of the second conductivity type is formed, characterized in accordance with the invention in that a part of the further semiconductor region adjoining the substrate is provided with a doping concentration which is higher than the doping concentration in the remaining part of the further semiconductor region. In this manner, a device in accordance with the invention is obtained in a simple manner.
Preferably, a part of the collector region adjoining the substrate is provided with a higher doping concentration than the remaining part of the collector region, which is partly formed by the further semiconductor region, and the doping concentration of the part of the further semiconductor region adjoining the substrate is chosen to be smaller than the doping concentration of the part of the collector region adjoining the substrate. The parts of the collector region adjoining the substrate and the further semiconductor region are preferably formed in the same process step. In accordance with the invention, this is achieved in that the part of the further semiconductor region adjoining the substrate is formed by a number of mutually separated sub-regions which are interconnected by means of a thermal treatment. In a preferred embodiment of a method in accordance with the invention, the semiconductor body provided with another semiconductor region, which is recessed therein, and which is of the first conductivity type and connected to the substrate, said semiconductor region being provided with another connection conductor and being positioned, preferably, as close as possible to the active region of the transistor.
These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.